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Engineer/Senior Engineer /Lead(Physical Design)

* Responsible for full chip implementation of complex SoCs .RTL-to-GDSII.* Work on Place and Route in 45nm and 28nm technologies* ......oor plan, including pin...... View More..

Physical Design Engineer

Job Responsibilities:- Responsible for full chip implementation of complex SoCs .RTL-to-GDSII. Work on Place and Route in 45nm and 28nm ......oor plan, including pin...... View More..

Free classifieds in Odisha

Odisha's best Local Search Engine Portal provides updated information on all B2B & B2C business across Odisha. Free classifieds in ......tments, houses, PG, jobs......jobs......jobs...... View More..

Staff Engineer - Program Management

Conceives and develops solutions to engineering programs through the application of professionally accepted engineering techniques, practices and procedures.Responsible for definition, ......ve familiarity with chip......ckground in leading chip......duct reliability. chip...... View More..

Software Intern

Software Intern 769067 Description This position is in the Platform Engineering Group .PEG.. PEG charged with creating an SoC .System ......Chip......chool, internships, jobs...... View More..

Placement Officer

-Be able to understand the requirements of students, their level/acumen & get them placed accordingly in companies the students would ......etc. in Tier 1.blue chip......dates are placed in jobs...... View More..

DV- Design and Verification Engr/ Lead

Job DescriptionPerform design verification .DV. at module/chip levels for complex and high-gate count radio SoC in TIs growing HSP organization. ......integrated in radio chip......lans for the module/chip......on for a successful chip...... View More..

Analog Integration Engineer

This candidate will work on complex IC designs for next generations of 32-bit microcontrollers.Job responsibilities include working with the chip ......locks, mixed-signal chip......egrity.Prepare full chip......stem level and full chip...... View More..

Analog Integration Engineer Electronics

This candidate will work on complex IC designs for next generations of 32-bit microcontrollers.Job responsibilities include working with the chip ......locks, mixed-signal chip......egrity.Prepare full chip......stem level and full chip...... View More..

Analog Integration Engineer

Job DescriptionAnalog Verification/Integration Engineer for the MCU32 design group in Bangalore. This candidate will work on complex IC designs for ......de working with the chip......locks, mixed-signal chip......egrity.Prepare full chip...... View More..

ENGINEER - CHIP DESIGN ADVANCED

Should have worked at IPlevel, Sub System level and SoC level in Specman eRM/System Verilog OVM/UVM,Should have worked at defining the Test Bench Architecture, developed Test Plan and developed Vectors, View More..

SENIOR ENGINEER - CHIP DESIGN ADVANCED

Should have worked at IPlevel, Sub System level and SoC level in Specman eRM/System Verilog OVM/UVM,Should have worked at defining the Test Bench Architecture, developed Test Plan and developed Vectors, View More..

ANALOG INTEGRATION ENGINEER

Job Description: Analog Verification/Integration Engineer for the MCU32 design group in Bangalore. This candidate will work on complex IC designs ......de working with the chip......locks, mixed-signal chip......grity. Prepare full chip...... View More..

EDA - Tool & Methodology Development Engineer

EDA .Electronic Design Automation. Engineering Professionals develop, specify or support software applications .aka EDA tools. to be used in controlled ......ning and synthesis; chip......gnoff and analysis; chip...... Development group, Chip...... View More..

EDA - Tool & Methodology Development Engineer

EDA .Electronic Design Automation. Engineering Professionals develop, specify or support software applications .aka EDA tools. to be used in controlled ......ning and synthesis; chip......gnoff and analysis; chip...... Development group, Chip...... View More..

SENIOR ENGINEER - CHIP DESIGN ADVANCED

Should have worked at IPlevel, Sub System level and SoC level in Specman eRM/System Verilog OVM/UVM,Should have worked at defining the Test Bench Architecture, developed Test Plan and developed Vectors, View More..

Chip design and verification engineers

Job Description :-Work on all aspects of physical design including synthesis, floor planning, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity analysis, physical verification, View More..

Computer Chip Level Servicing in Chennai

Computer Chip Level Servicing in Chennai Contact our customer support: +091-xxxxxxxxxx / +091-xxxxxxxxxx /044 42139995/ +091-xxxxxxxxxx Laptop chip level repairing within ......u, and more. Chip...... View More..

ENGINEER - CHIP DESIGN ADVANCED

Strong knowledge of DFT including JTAG, MBIST, scan, on-chip scan compression, fault models, ATPG, and fault simulation and AC scan ...... Experience in Full-Chip...... View More..